The present invention relates to a stack package, and more particularly to a through-silicon via for connection of stacked chips and a method for forming the same.
Packaging technology for an integrated circuit has continuously been developed to meet the demand toward miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric/electronic products are required, various techniques have been disclosed in the art.
The term “stack” in the semiconductor industry means a vertical stand or pile of at least two chips or packages, one atop the other. By using a stack, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is two times greater than that obtainable through semiconductor integration processes. Also, a stack package provides advantages not only through an increase in memory capacity but also in view of a mounting density and mounting area utilization efficiency. Due to this fact, researches and development for a stack package have been accelerated.
As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art. The stack package using a TSV has a structure in which the TSV is formed in a chip so that chips are physically and electrically connected with each other through the TSV. A method for forming the TSV is as described below.
A vertical hole is defined through a predetermined portion of each chip at a wafer level. An insulation layer is formed on the surface of the vertical hole. With a seed metal layer formed on the insulation layer, an electrolytic substance, that is, a metal is filled into the vertical hole through an electroplating process to form a TSV. Then, the TSV is exposed through back-grinding of the backside of a wafer.
After the wafer is sawed and is separated into individual chips, at least two chips can be vertically stacked, one atop the other, on one of the substrates using one or more of the TSV. Thereupon, the upper surface of the substrate including the stacked chips is molded, and solder balls are mounted on the lower surface of the substrate, by which the manufacture of a stack package is completed.
In this type of stacked package using a TSV, when filling the vertical hole, in order to prevent the diffusion of the electrolytic substance, the insulation layer is formed on the surface of the vertical hole.
It is the norm that the insulation layer uses an oxide layer, which is formed through a high-temperature dry oxidization and wet oxidization processes or a nitride layer. The oxide layer formed through the high-temperature dry oxidization and wet oxidization processes or the nitride layer is relatively expensive. Also, while a proper thickness is required to secure an insulation characteristic, when considering the size of the vertical hole, it is difficult to secure a thickness for obtaining a satisfactory insulation characteristic. In addition, since the layer must be formed in the vertical hole, it is difficult to obtain uniformity and low roughness.
Moreover, the oxide layer formed through the high temperature dry oxidization and wet oxidization processes or the nitride layer is difficult to compensate for a difference in mechanical characteristic between the electrolytic substance in the vertical hole and silicon. As is known, a semiconductor chips generate heat while operating. Different thermal expansion coefficients between silicon and a metal or metallic substance can causes stresses in a semiconductor chip as its temperature rises and falls during operation, which is a phenomena that can significantly deteriorate the integrity and hence the reliability of silicon/metal junctions in a chip during the operation of the semiconductor chip. As a consequence, if the insulation layer cannot relieve the fatigue caused due to the difference in thermal expansion coefficient, displacements of respective materials vary when operation temperature is changed, and a fatigue is caused, by which fracture of a package may result. In this regard, the oxide layer or the nitride layer cannot appropriately relieve the fatigue caused due to the difference in thermal expansion coefficient between materials, as a result of which the fracture of the package may not be avoided.
Furthermore, in the oxide layer formed through the high temperature dry oxidization and wet oxidization processes or the nitride layer, when a defect is produced therein, a crack starting from the defect can be easily propagated into silicon, thereby causing a defect in a chip.